>Design and fabrication of high performance wafer-level vacuum packaging based on glass–silicon–glass bonding techniques
In this paper, a high performance wafer-level vacuum packaging technology based on GSG triple-layer sealing structure for encapsulating large mass inertial MEMS devices fabricated by silicon-on-glass bulk micromachining technology is presented. Roughness controlling strategy of bonding surfaces was proposed and described in detail. Silicon substrate was thinned and polished by CMP after the first bonding with the glass substrate and was then bonded with the glass micro-cap. Zr thin film was embedded into the concave of the micro-cap by a shadow-mask technique. The glass substrate was thinned to about 100 µm, wet etched through and metalized for realizing vertical feedthrough. During the fabrication, all patterning processes were operated carefully so as to reduce extrusive fragments to as little as possible. In addition, a high-performance micro-Pirani vacuum gauge was integrated into the package for monitoring the pressure and the leak rate further. The result shows that the pressure in the package is about 120 Pa and has no obvious change for more than one year indicating 10−13 stdcc s−1 leak rate.
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